NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 456
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NUC100LC1BN
Manufacturer Part Number
NUC100LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC100LC1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Host-to-Device:
First of all, the PS/2 device always generates the CLK signal. If the host wants to send DATA, it
must first put the CLK and DATA lines in a "Request-to-send" state as follows:
The device should check for this state at intervals not to exceed 10 milliseconds. When the device
detects this state, it will begin generating CLK signals and CLK in eight DATA bits and one stop
bit. The host changes the DATA line only when the CLK line is low, and DATA is read by the
device when CLK is high.
After the stop bit is received, the device will acknowledge the received byte by bringing the DATA
line low and generating one last CLK pulse. If the host does not release the DATA line after the
11th CLK pulse, the device will continue to generate CLK pulses until the DATA line is released.
CLK
DATA
CLK
Inhibit communication by pulling CLK low for at least 100 microseconds
Apply "Request-to-send" by pulling DATA low, then release CLK
DATA
NuMicro™ NUC100 Series Technical Reference Manual
Figure 5-84 Data Format of Device-to-Host
Figure 5-85 Data Format of Host-to-Device
- 456 -
Publication Release Date: Dec. 22, 2010
Revision V1.06
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