NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 196

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.3.8
Power Down Control Register （PWRCON）
Except the BIT[6], all the other bits are protected, program these bits need to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100
Register
PWRCON
Bits
[31:9]
[8]
[7]
PWR_DOWN
Register Description
_EN
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
CLK_BA+0x00
Descriptions
Reserved
PD_WAIT_CPU
PWR_DOWN_EN
PD_WU_STS
30
22
14
6
PD_WU_INT_
R/W
R/W
Reserve
This bit control the power down entry condition (write-protection bit)
1 = Chip enter power down mode when the both PWR_DOWN_EN bit is set to 1 and
0 = Chip entry power down mode when the PWR_DOWN_EN bit is set to 1
System power down enable bit (write-protection bit)
When CPU sets this bit to 1, the chip power down mode is enabled and chip power-
down behavior will depends on the PD_WAIT_CPU bit
(a) If the PD_WAIT_CPU is 0, then the chip enters power down mode immediately
(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is
When chip wakes up from power down mode, this bit is auto cleared. Users need to set
this bit again for next power down.
When in power down mode, external 4~24 MHz crystal and the internal 22.1184 MHz
oscillator will be disabled in this mode, but the external 32 kHz crystal and internal 10
kHz oscillator are not controlled by power down mode.
When in power down mode, the PLL and system clock are disabled, and ignored the
clock source selection. The clocks of peripheral are not controlled by power down
mode, if the peripheral clock source is from external 32 kHz crystal or the internal 10
kHz oscillator.
EN
29
21
13
5
CPU run WFI instruction.
after the PWR_DOWN_EN bit set.
also active and then the chip enters power down mode
Description
System Power Down Control Register
PD_WU_DLY OSC10K_EN OSC22M_EN XTL32K_EN
Reserved
28
20
12
4
- 196 -
Reserved
Reserved
27
19
11
3
Publication Release Date: Dec. 22, 2010
26
18
10
2
25
17
9
1
Revision V1.06
Reset Value
0x0000_001X
PD_WAIT_CP
XTL12M_EN
24
16
U
8
0