s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 126

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

INSTRUCTION SET
OPERATION
The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the
following table.
NOTE: The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0),
INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-18. The instruction cycle
times for the THUMB instruction are identical to that of the equivalent ARM instruction.
Examples
3-84
FORMAT 11: SP-RELATIVE LOAD/STORE
L
0
1
STR Rd, [SP, #Imm]
LDR Rd, [SP, #Imm]
THUMB Assembler
since the assembler places #Imm >> 2 in the Word8 field.
15
1
STR
14
0
13
0
R4, [SP,#492]
12
1
STR Rd, [R13 #Imm]
LDR Rd, [R13 #Imm]
Table 3-18. SP-Relative Load/Store Instructions
ARM Equivalent
11
L
10
[7:0] Immediate Value
[10:8] Destination Register
[11] Load/Store Bit
0 = Store to memory
1 = Load from memory
Figure 3-40. Format 11
Rd
8
; Store the contents of R4 at the address
; formed by adding 492 to SP (R13).
; Note that the THUMB opcode will contain
; 123 as the Word8 value.
Add unsigned offset (255 words, 1020 bytes) in Imm to
the current value of the SP (R7). Store the contents of
Rd at the resulting address.
Add unsigned offset (255 words, 1020 bytes) in Imm to
the current value of the SP (R7). Load the word from the
resulting address into Rd.
7
Word 8
Action
0
S3C4510B