s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 283

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
Reporting of Receive Errors
When it detects a start of frame delimiter (SFD), the receive state machine starts putting data it has received
from the MII into the receive FIFO. It also checks for internal errors (FIFO overruns) while reception is in
progress.
When the receive operation is completed, the receive state machine checks for external errors, such as frame
alignment, length, CRC, and frame too long.
The following is a description of the types of errors that may occur during a receive operation:
Priority error
Frame Alignment Error
CRC Error
Frame too long
Receive FIFO overrun
MII error
A parity bit protects each byte in the MAC receive FIFO. If a parity error occurs,
it is reported to the receive state machine. A detected parity error sets the RxPar
bit in the receive status register.
(Dribble)
After receiving a packet, the receive block checks that the incoming packet
(including CRC) was correctly framed on an 8-bit boundary. If it is not and if the
CRC is invalid, data has been disrupted through the network, and the receive
block reports a frame alignment error. A CRC error is also reported.
After receiving a packet, the receive block checks the CRC for validity, and
reports a CRC error if it is invalid. The receive unit can detect network-related
errors such as CRC, frame alignment, and length errors. It can also detect these
types of errors in the following combinations:
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The receive block checks the length of the incoming packet at the end of
reception (including CRC, but excluding preamble and SFD). If the length is
longer than the maximum frame size of 1518 bytes, the receive block reports
receiving a "long packet", unless long frame mode is enabled.
During reception, the incoming data are put into the receive FIFO temporarily
before they are transferred to the system memory. If the FIFO is filled up
because of excessive system latency or for other reasons, the receive block sets
the overrun bit in the receive status register.
The PHY informs the MAC if it detects a medium error (such as a coding
violation) by asserting the input pin Rx_er. When the MAC sees Rx_er asserted,
it sets CRCErr bit of the receive status register.
CRC errors only
Length and CRC errors only
Frame alignment and CRC errors only
Frame alignment, length, and CRC errors
ETHERNET CONTROLLER
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