s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 353

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
DEMAND AND ONE DATA BURST MODE (GDMACON[15] = 1, [9] = 0 )
DREQ and DACK signals are active low.
DEMAND & FOUR DATA BURST MODE ( GDMACON[15] = 1, [9] = 1 )
This timing diagram is the same with Demand & one data burst exception four data burst.
one data burst; source address0 and source data0
four data burst; source address0 and source data0
If you want to use continuous mode, you must set block mode not single mode.
If you want to use demand mode, you must set single mode not block mode.
In_MCLK
Address
GDMA
DREQ
DACK
Data
CNT
source data2
destination address2 and destination data2
NOTE:
destination address1 and destination data1
S# is source address#, and D# is destination address#.
If GDMA CNT is zero, GDMAC do not transfer data although DREQ signal asserted.
Figure 9-15. Demand and One Data Burst Mode Timing
source address3 and source data3
S0
8
D0
7
S1
6
destination address0 and destination data0
NOTE
source address1 and source data1
D1
5
S2
4
destination address3 and destination data3
destination address2 and destination data2
D2
3
destination address0 and destination data0
2
S3
D3
1
source address2 and
DMA CONTROLLER
0
...
...
9-17