s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 274

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
MII TRANSMIT OPERATION
The transmit block consists of three state machines: the gap_ok state machine, the back_off state machine, and
the main transmit state machine.
The gap_ok State Machine
The gap_ok state machine tracks and counts the inter-gap timing between the frames. When not operating in
full-duplex mode, it counts 96 bit times from the deassertion of the carrier sense (CrS) signal. If there is any
traffic within the first 64 bit times, the gap_ok state machine reset itself and starts counting from zero.
If there is any traffic in the last 1/3 of the inter-frame gap, the gap_ok state machine continues counting.
Following a successful transmission, a gap_ok is sent at the end of the next 96 bit times, regardless of the
network traffic.
In full-duplex mode, the gap_ok state machine starts counting at the end of the transmission and the gap_ok
signal is sent at the end of the 96 bit times, regardless of the network traffic.
7-52
Yes
Wait for back-off time:
(=slot time x r),
k = minimum (n, back-off limit (=10))
0<=n <Max_attempt (=16)
0<= random integer (r) <= 2k
Wait for interframe gap
Assemble MAC frame
with preamble + SFD
(96-bit time), start Tx
Carrier sense==ON?
Done. Complete Tx
Collision detected?
Figure 7-18. CSMA/CD Transmit Operation
Yes
Report attempt limit
Preamble and SFD
Stop transmission,
++ Attemp_count
Attempt_count>=
send 32-bit jam,
exceeded error
Max_attempt?
transmission
transmitted?
Continue
Yes
Yes
; To upper level layer
S3C4510B