s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 299

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s3c4510b

Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C4510B
HDLC DATA SETUP AND HOLD TIMING WITH CLOCK
You can see the timing of TxD and RxD in terms of TxC and RxC HDLC clock in Figure 8-6.
Tx data will be sent with delayed 9.82 nsec to 10.66 nsec from the falling edge of Tx Clock. In case of RxD, the
black period should not be changed. That is, the RxD should be stable from 0.2nsec to 1.0nsec after RxC rising
edge. (It does not allow data transition during this period) The RxC will be Rx(receiver) clock through Rx clock
selection part with some delay. And this RxC delay is larger then RxD delay. In Figure 8-6, the dotted-clock is
real internal Rx clock used by the receiver. Therefore, there should not be transit in Rx data to avoid setup or
hold violation.
TxC
TxD
RxC
RxD
Symbol
Ttxdf
Trxdf
TxD falling edge delay time
TxD falling edge delay time
Figure 8-6. Data Encoding Methods and Timing Diagrams
Table 8-3. HMODEA and HMODEB Register
0.2 ns
Condition
1.0 ns
40
9.82
ns
ns
9.82
Min
1.0
10.66
Typ
ns
HDLC CONTROLLERS
10.66
Max
Unit
ns
ns
8-13

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