s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 223
s3c4510b
Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C4510B.pdf
(422 pages)
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S3C4510B
ETHERNET CONTROLLER
7
ETHERNET CONTROLLER
OVERVIEW
The S3C4510B has an ethernet controller which operates at either 100-Mbits or 10-Mbits per second in half-
duplex or full-duplex mode. In half-duplex mode, the controller supports the IEEE 802.3 carrier sense multiple
access with collision detection (CSMA/CD) protocol. In full-duplex mode, it supports the IEEE 802.3 MAC control
layer, including the pause operation for flow control.
The ethernet controller s MAC layer supports both the media independent interface (MII) and the buffered DMA
interface (BDI). The MAC layer itself consists of the receive and the transmit blocks, a flow control block, a
content addressable memory (CAM) for storing network addresses, and a number of command, status, and error
counter registers.
The MII supplies the transmit and receive clocks of 25 MHz for 100-Mbit/s operation or 2.5 MHz at the 10-Mbit/s
speed. The MII conforms to the ISO/IEC 802-3 standards for a media-independent layer which separates
physical layer issues from the MAC layer.
7-1
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