s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 315

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
HDLC CONTROL REGISTER
Number
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
Registers
HCONA
HCONB
Tx reset (TxRS)
Rx reset (RxRS)
DMA Tx reset (DTxRS)
DMA Rx reset (DRxRS) Set this bit to '1' to reset the DMA Rx block.
Tx enable (TxEN)
Rx enable (RxEN)
DMA Tx enable
(DTxEN)
Bit Name
0 7004
0x8004
Offset
Table 8-8. HCONA and HCONB Register
Table 8-9. HCON Register Description
Set this bit to '1' to reset the Tx block. Tx block comprises HTxFIFO and a
transmitter block.
Set this bit to '1' to reset the Rx block. Rx block comprises HRXFIFO and a
receiver block.
Set this bit to '1' to reset the DMA Tx block.
When the TxEN bit is '0', the transmitter enters a disabled state and the
line becomes high state. In this case, the transmitter block is cleared
except for the HTxFIFO and the status bits associated with transmit
operation are cleared. Data cannot be loaded into the HTxFIFO.
If this bit is set to '1', the idle pattern is sent continuously. In this case, the
data can be loaded into HTxFIFO, and then sent.
When the RxEN bit is '0', the receiver enters a disabled state and can not
detect the flag pattern, if any. In this case, receiver block is cleared except
for the HRXFIFO and the status bits associated with receiver operation are
cleared. Data cannot be received.
If this bit is set to '1', the flag pattern is detected. In this case, the data
received can be loaded into the HRXFIFO, and moved to system memory.
The DTxEN bit lets the HDLC Tx operate on a bus system in DMA mode.
When DMA Tx is enabled, an interrupt request caused by TxFA status is
inhibited and the HDLC does not use the interrupt request to request a data
transfer. DMA Tx monitors the HTxFIFO and fills the HTxFIFO. This bit is
auto disabled when Tx underrun occurs, or CTS lost, or next buffer
descriptor pointer reach null, or the owner bit is not DMA mode when
DTxSTSK bit is set. If Tx underrun occurs, DTxABT(in HSTAT) bit set, and
abort signal sended. If CTS lost occurs, DTxABT bit set and TxD output
goes high state as long as CTS remains high level.
R/W
R/W
R/W
HDLC channel A control register
HDLC channel B control register
Description
Description
HDLC CONTROLLERS
Reset Value
0x00000000
0x00000000
8-29