s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 238

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
S3C4510B
DATA FRAMES
The ownership bit in the MSB of the frame start address controls the owner of the descriptor. When the
ownership bit is "1", the BDMA controller owns the descriptor. When this bit is "0", the CPU owns the descriptor.
The owner of the descriptor always owns the associated data frame. (The descriptor's frame start address field
always points to this frame.)
As it receives the data frame, software sets the maximum frame size register in the BDMA block to the system
frame buffer size (typically, to 1536 or 2048). Software also sets the Rx frame descriptor start address register to
point to a chain of frame descriptors, all of which have their ownership bit set.
The BDMA engine can then be started to set the BDMA receive enable bit in the BDMARXCON register. When a
frame is received, it is copied into memory at the address specified by the Rx frame start address. Please note
that no configurable offset or page boundary calculation is required. The received frame is written into the frame
data buffer until the end of frame is reached, or until the length exceeds the configured maximum frame size.
If the entire frame is received successfully, the status bits in the frame descriptor are set to indicate this.
Otherwise, the status bits are set to indicate that an error occurred. The ownership bit in the frame start address
field is cleared and an interrupt may now be generated. The BDMA controller copies the next frame descriptor
register value into the Rx frame descriptor start address register. If the next frame descriptor address is null (0),
the BDMA simply halts, and all subsequent frames are dropped. Otherwise, the descriptor is read in, and the
BDMA controller starts again with the next frame, as described in the previous paragraph.
If the received frame size exceeds the maximum frame size, the data frame will be overwritten by the last word
of maximum frame. The overflow data is written to the Rx status bit [19] in the receive frame descriptor. When
the BDMA reads a descriptor, if the ownership bit is not set, it has two options:
— Skip to the next frame descriptor, or
— Generate an interrupt and halt the BDMA operation.
Transmit frame descriptors contain the following components:
— A four-byte pointer to the frame data
— Widget alignment control bits [6:5]
— Frame data pointer increment/decrement bit [4]
— Little-Endian control bit [3]
— Interrupt enable after transmit [2]
— No-CRC [1], and
— No-padding [0]
During transmission, the two-byte frame length at the Tx frame descriptor is moved into the BDMA internal Tx
register. After transmission, Tx status is saved in the Tx frame descriptor. The BDMA controller then updates the
next frame descriptor address register for the linked list structure.
When the Tx frame descriptor start address register points to the first frame buffer, transmitter starts transmitting
the frame data into the frame buffer memory.
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