s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 208
![no-image](/images/no-image-200.jpg)
s3c4510b
Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C4510B.pdf
(422 pages)
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UNIFIED INSTRUCTION/DATA CACHE
5-2
100: Set 0 direct access
101: Set 1 direct access
110: TAG direct access
31
Set I Cache 1 = 4 instruction/data (128-bit)
Instr3
30 29
28
27
(Set 0 Hit)
(Set 1 Hit)
Instr2
Figure 5-1. Memory Configuration for 4-Kbyte (or 8-Kbyte) Cache
26
2
25
Enable non-cacheable control
Instr1
32-bit
2
CS
32
Tag Address (15-bit)
Set 1 Tag
Instr0
Tag RAM (32-bit)
15 (14)
switch
32
Set I Cache 0 = 4 instruction/data (128-bit)
Instr3
15 (14)
Set 0 Tag
32
15 (14)
Instr2
10 9
Height = 128 (256)
Instr1
32-bit
Decoder
7 (8) bits
Instr0
4 3 2 1
7 (8)-bit
2-bit
2
7 (8)-bit
Height =
128 (256)
0
S3C4510B
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