s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 362

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

UART
UART STATUS REGISTER
10-8
USTAT0
USTAT1
Bit Number
Registers
[0]
[1]
[2]
[3]
[4]
Offset Address
Overrun error
Parity error
Frame error
Break interrupt
Data terminal ready
(DTR)
0xD008
0xE008
Bit Name
Table 10-7. UART Status Register Description
Table 10-6. UCON0 and UCON1 Registers
R/W
R
R
USTAT[0] is automatically set to "1" whenever an overrun error
occurs during a serial data receive operation. The overrun error
indicates that the new received data has overwritten old received
data before the old data could be read.
If the receive status interrupt enable bit, UCON[2] is "1", a receive
status interrupt is generated if an overrun error occurs.
This bit is automatically cleared to "0" whenever the UART status
register (USTAT) is read.
USTAT[1] is automatically set to "1" whenever a parity error occurs
during a serial data receive operation. If the receive status interrupt
enable bit, UCON[2], is "1", a receive status interrupt is generated
if a parity error occurs.
This bit is automatically cleared to "0" whenever the UART status
register (USTAT) is read.
USTAT[2] is automatically set to "1" whenever a frame error occurs
during a serial data receive operation. A frame error occurs when a
zero is detected instead of the Stop bit(s).
If the receive status interrupt enable bit, UCON[2] is "1", a receive
status interrupt is generated if a frame error occurs.
The frame error bit is automatically cleared to "0" whenever the
UART status register (USTAT) is read.
USTAT[3] is automatically set to "1" to indicate that a break signal
has been received.
If the receive status interrupt enable bit, UCON[2], is "1", a receive
status interrupt is generated if a break occurs.
The break interrupt bit is automatically cleared to "0" when you
read the UART status register.
The USTAT[4] bit indicates the current signal level at the data
terminal ready (DTR) pins (nUADTR). When this bit is "1", the level
at the DTR pin (nUADTR) is Low. When it is "0", the DTR pin is
High level.
UART0 status register
UART1 status register
Description
Reset Value
Reset Value
0xC0
0xC0
S3C4510B