s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 209

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s3c4510b

Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C4510B
CACHE REPLACE OPERATIONS
When the contents of two sets are valid and when the content of the cache must be replaced due to a cache
miss, the CS value becomes "10" at specified line. This indicates that the content of set 0 (S0) was replaced.
When CS is "10" and when another replacement is required due to a cache miss, the content of set 1 (S1) is
replaced by changing the CS value to "01".
To summarise, at its normal steady state, the CS value is changed from "01" or "10" to "10" or "01". This
modification provides the information necessary to implement a 2-bit pseudo-LRU (Least Recently Used) cache
replacement policy.
Hit 1
Reset(/)
NVALID: 00
AV-S1D: 11
S0 only: 01
miss
miss
Miss or hit 1
Miss or hit 0
Figure 5-2. Cache Replace Algorithm State Diagram
Hit
AV-S0D: 10
Hit 0
; Set 0, set 1 all invalid
; Chahe miss occurs
; Set 0 = valid, set 1 = invalid
; Read miss
; AV_S1D = All valid and set 1 is dirty.
; AV_S0D = All valid and set 0 is dirty.
Status does not change on hit
Dirty means to access just before;
status does not change on hit.
UNIFIED INSTRUCTION/DATA CACHE
5-3

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