s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 17

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
CPU CORE OVERVIEW
The S3C4510B CPU core is a general purpose 32-bit ARM7TDMI microprocessor, developed by Advanced RISC
Machines, Ltd. (ARM). The core architecture is based on Reduced Instruction Set Computer (RISC) principles.
The RISC architecture makes the instruction set and its related decoding mechanism simpler and more efficient
than those with microprogrammed Complex Instruction Set Computer (CISC) systems. High instruction
throughput and impressive real-time interrupt response are among the major beneifts of the architecture.
Pipelining is also employed so that all components of the processing and memory systems can operate
continuously. The ARM7TDMI has a 32-bit address bus.
An important feature of the ARM7TDMI processor that makes itself distinct from the ARM7 processor is a unique
architectural strategy called THUMB. The THUMB strategy is an extension of the basic ARM architecture
consisting of 36 instruction formats. These formats are based on the standard 32-bit ARM instruction set, while
having been re-coded using 16-bit wide opcodes.
As THUMB instructions are one-half the bit width of normal ARM instructions, they produce very high-density
codes. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent
instruction in the standard ARM instruction set. The ARM core then processes the 16-bit instruction as it would a
normal 32-bit instruction. In other words, the THUMB architecture gives 16-bit systems a way to access the 32-bit
performance of the ARM core without requiring the full overhead of 32-bit processing.
As the ARM7TDMI core can execute both standard 32-bit ARM instructions and 16-bit THUMB instructions, it
allows you to mix the routines of THUMB instructions and ARM code in the same address space. In this way, you
can adjust code size and performance, routine by routine, to find the best programming solution for a specific
application.
Figure 1-4. ARM7TDMI Core Block Diagram
Register Bank
Incrementer
Write Data
Address
Register
Address
Register
32-Bit ALU
Multiplier
Shifter
Barrel
Pipeline and Read
Logic Controll
Data Register
Decoder and
Instruction
Instruction
PRODUCT OVERVIEW
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