s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 148

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

SYSTEM MANAGER
EXTERNAL ADDRESS TRANSLATION METHOD DEPENDS ON THE WIDTH OF EXTERNAL MEMORY
The S3C4510B address bus is, in some respects, different than the bus used in other standard CPUs. Based on
the required data bus width of each memory bank, the internal system address bus is shifted out to an external
address bus, ADDR[21:0]. This means that memory control signals such as nRAS[3:0], nCAS[3:0], nECS[3:0],
nRCS[5:0], and nWBE[3:0] are generated by the system manager according to a pre-configured external memory
scheme (see Table 4-2). This is applied to SDRAM signals as same method.
4-6
Data Bus Width
16-bit
32-bit
8-bit
External Address Pins
ADDR [21:0]
External Address Pins, ADDR[21:0]
Table 4-2. Address Bus Generation Guidelines
Figure 4-3. External Address Bus Diagram
A21–A0 (internal)
A22–A1 (internal)
A23–A2 (internal)
22-bit
16-bit
32-bit
8-bit
System Address Bus: SA [25:0]
Data Bus Width Configuration
22-bit
22-bit
22-bit
(8-bit/16-bit/32-bit)
Accessible Memory Size
4M half-words
SA [21:0]
SA [22:1]
SA [23:2]
4M words
4M bytes
S3C4510B