s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 262

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
MAC Receive Status Register
A receive status flag is set in the MAC receive status register, MACRXSTAT, whenever the corresponding event
occurs. When a status flag is set, it remains set until another packet arrives, or until software writes a "1" to the
flag to clear the status bit. If the corresponding interrupt enable bit in the receive control register is set, an
interrupt is generated whenever a status flag is set. A MAC receive parity error sets RxPar, and also clears the
RxEn bit (if an interrupt is enabled).
7-40
MACRXSTAT
Bit Number
Registers
[31:16]
[4:0]
[10]
[11]
[12]
[13]
[14]
[15]
[5]
[6]
[7]
[8]
[9]
Reserved
Control frame received (CtlRecd) This bit is set if the packet received is a MAC control frame
Interrupt on receive (IntRx)
Receive 10-Mb/s status
(Rx10Stat)
Alignment error (AlignErr)
CRC error (CRCErr)
Overflow error (overflow)
Long error (LongErr)
Reserved
Receive parity error (RxPar)
Good received (Good)
Reception halted (RxHalted)
Reserved
0XA014
Offset
Table 7-29. MAC Receive Status Register Description
Bit Name
Table 7-28. MACRXSTAT Register
R/W
R/W
Receive status
Not applicable.
(type = 8808H), if the CAM recognizes the packet address,
and if the frame length is 64 bytes.
This bit is set if the reception of a packet caused an
interrupt to be generated. This includes a good received
interrupt, if the EnGood bit is set.
This bit is set to "1" if a packet was received over the 7-wire
interface or to "0" if a packet was received over the MII.
This bit is set if the frame length in bits was not a multiple of
eight and the CRC was invalid.
This bit is set if the CRC at the end of a packet did not
match the computed value, or else the PHY asserted Rx_er
during packet reception.
This bit is set if the MAC receive FIFO was full when it
needed to store a received byte.
This bit is set if the MAC received a frame longer than 1518
bytes. (It is not set if the long enable bit in the receive
control register, MACRXCON, is set.)
Not applicable.
This bit is set if a parity error is detected in the MAC receive
FIFO.
This bit is set if a packet was successfully received with no
errors. If EnGood = "1", an interrupt is also generated.
This bit is set if reception was halted by clearing RxEn or by
setting the HaltImm bit in the MAC control register,
MACON.
Not applicable.
Description
Description
Reset Value
0x00000000
S3C4510B