s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 351

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
BLOCK AND ONE DATA BURST MODE (GDMACON[11] = 1, [9] = 0 )
DREQ and DACK signals are active low.
GDMAC transfers data from DREQ signal is active till GDMA COUNT Register consumes.
BLOCK AND FOUR DATA BURST (GDMACON[11] = 1, [9] = 1 )
This timing diagram is the same with Single and one data burst exception four data burst.
one data burst; source address0 and source data0
four data burst; source address0 and source data0
In_MCLK
In the four data burst mode, GDMA COUNT Register value decreases by 1 after 4 data transfer.
Address
DREQ
DACK
Data
NOTE:
source data2
destination address3 and destination data3
'¨Í' is in the block mode, GDMAC starts to operate with first DREQ signal. So in the ideal case,
GDMAC don't care the number of DREQ signal pulse. But I recommand that DREQ siganl is
deasserted when DACK signal is active state.
destination address1 and destination data1
Figure 9-13. Block and One Data Burst Mode Timing
source address3 and source data3
Address
Source
Source
Data
Destination
Address
Destination
NOTE
a
destination address0 and destination data0
source address1 and source data1
Data
Recommand
Deasserted Time
source address4 and source data4
destination address2 and destination data2
destination address0 and destination data0
Address
Source
Source
Data
source address2 and
Destination
Address
DMA CONTROLLER
Destination
Data
....
....
9-15