s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 191

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
DRAMCON#
31
CAN
30 29
DRAM Bank # Next Pointer
Figure 4-29. DRAM Control Registers (DRAMCON–DRAMCON3)
[0] EDO mode (EDO)
0 = Normal DRAM (Fast page mode DRAM)
1 = EDO DRAM
[2:1] CAS strobe time (tCS)
00 = 1 cycle
10 = 3 cycles
[3:3] CAS pre-charge time (tCP)
0 = 1 cycle
[6:4] Reserved
These bits default value is 000. But, you must set to 001.
[7] RAS to CAS delay (tRC or tRCD)
0 = 1 cycle
[9:8] RAS pre-charge time (tRP)
00 = 1 cycle
10 = 3 cycles
[19:10] DRAM bank # base pointer
This value indicates the start address of DRAM bank #. The start address is
calculated as RAM bank # base pointer << 16
[29:20] DRAM bank # next pointer
This value is the current bank end address << 16 + 1
[31:30] Number of column address bits in DRAM bank # (CAN)
00 = 8 bits
10 = 10 bits
NOTE:
In SDRAM mode, this bit affect SDRAM cycle.
tCS value[1]: 0 = 1 cycle
20
1 = 2 cycle
19
DRAM Bank # Base Pointer
01 = 2 cycles
11 = 4 cycles
1 = 2 cycles
1 = 2 cycles
01 = 2 cycles
11 = 4 cycles
01 = 9 bits
11 = 11 bits
(note)
10
9
tRP
8
R
C
7
t
Reserve
6
SYSTEM MANAGER
4
C
P
3
t
2
tCS
1
4-49
E
D
O
0