s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 364

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s3c4510b

Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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UART
10-10
31
[0] Overrun error (OV)
0 = No overrun error during receive
1 = Overrun error (generate receive status interrupt if UCON[2] is 1)
[1] Parity error (PE)
0 = No parity error during receive
1 = Parity error (generate receive status interrupt if UCON[2] is 1)
[2] Frame error (FE)
0 = No frame error during receive
1 = Frame error (generate receive status interrupt if UCON[2] is 1)
[3] Break detect (BKD)
0 = No break received
1 = Break received (generate receive stauts interrupt if UCON[2] is 1)
[4] Data terminal ready (DTR)
0 = DTR pin (nUADTR) is High
1 = DTR pin (nUADTR) is Low
[5] Receive data ready (RDR)
0 = No vaild data in the receive buffer register
1 = Vaild data present in the receive buffer register
[6] Transmit buffer register empty (TBE)
0 = Vaild data in transmit holding register
1 = No data in transmit holdign register
[7] Transmit complete (TC)
0 = Transmit in progress
1 = Transmit complete; no data for Tx
(issue interrupt or DMa request if UCON[1:0] is set)
(as the setting of UCON[4:3], interrupt or GDMA request is generated)
Figure 10-4. UART Status Registers
8
C
7
T
B
E
6
T
R
D
R
5
D
R
4
T
B
K
D
3
E
2
F
P
E
1
O
V
0
S3C4510B

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