s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 401
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s3c4510b
Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C4510B.pdf
(422 pages)
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S3C4510B
BOUNDARY SCAN REGISTER
The S3C4510B scan chain implementation uses a 233-bit boundary scan register. This register contains bits for
all device signals and clock pins, and for associated control signals.
All bi-directional pins have two register bits in the boundary scan register for pin data. Each pin is controlled by
an associated control bit in the boundary scan register. The twenty-three bits in the boundary scan register define
the output enable signals for associated groups of bi-directional and tri-stateable pins. The control bits and their
bit positions are listed in Table B-1.
BOUNDARY SCAN DEFINITIONS
The boundary scan bit definitions are listed in Tables B-2 through B-5:
— The first column in the table defines the bit's ordinal position in the boundary scan register. The shift register
— The second column refers to one of the four S3C4510B cell types: jtin1, jtbi1, and jtout1.
— The third column lists the pin name of pin-related cells or defines the name of bi-directional control register
— The fourth column lists the pin type. TS-Output indicates a tri-stateable output pin, and OD-I/O denotes an
— The fifth column indicates the associated boundary scan register control bit for bi-directional, tri-state output.
cell nearest TDO (that is, the first bit to be shifted out) is defined as bit 0. The last bit to be shifted out is bit
number 232.
bits.
open-drain bi-directional pin.
penb [17]
penb [16]
penb [15]
penb [14]
penb [13]
penb [12]
penb [11]
penb [10]
Name
Bit Number
12
15
18
21
24
27
30
9
Table A-1. Boundary Scan Control Bits
penb [9]
penb [8]
penb [7]
penb [6]
penb [5]
penb [4]
penb [3]
penb [2]
Name
Bit Number
33
36
39
42
45
48
51
54
mdio_oe
penb [1]
penb [0]
dis_bus
txcben
txcaen
Name
d_enb
Bit Number
APPENDIX A
127
184
192
211
222
57
60
A-3
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