s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 245

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
Buffered DMA Transmit Control Register
The buffered DMA transmit control register, BDMATXCON, is described in Tables 7-3 and 7-4 below.
BDMATXCON
Bit Number
Registers
[13:11]
[4:0]
[10]
[5]
[6]
[7]
[8]
[9]
BDMA Tx burst size
(BTxBRST)
BDMA Tx stop/skip frame by
owner bit (BTxSTSKO)
Reserved
BDMA Tx complete to send
control packet interrupt enable
(BTxCCPIE)
BDMA Tx Null list interrupt
enable (BTxNLIE)
BDMA Tx not owner interrupt
enable (BTxNOIE)
BDMA Tx buffer empty
interrupt enable (BTxEmpty)
BDMA transmit to MAC Tx
start level (BTxMSL)
0x9000
Offset
Table 7-4. BDMA Transmit Control Register Description
Bit Name
Table 7-3. BDMATXCON Register
R/W
R/W
(Word size + 1) of data bursts requested in BDMA mode.
If the BTxBRST is zero, the burst size is one word.
If the BTxBRST is 31, the burst size is 32 words.
This bit determines whether the BDMA Tx controller issues an
interrupt, if enabled, or skips the current frame and goes to the
next frame descriptor (assuming BDMA is not the owner).
Not applicable.
Setting this bit enables the BDMA Tx complete to send contol
packet interrupt when the MAC has finished sending the
control packet.
This bit enables the BDMA Tx Null list interrupt which indicates
that the transmit frame descriptor start address pointer,
BDMATXPTR, in the BDMA Tx block has a null (0x00000000)
address.
This bit enables the BDMA Tx not owner interrupt when the
ownership bit of the current frame does not belong to the
BDMA controller, and if the BTxSTSKO bit is set.
Set this bit is "1" to enable the Tx buffer empty interrupt.
These bits determine when the new frame data in BDMA Tx
buffer can be moved to the MAC Tx FIFO when a new frame
arrives.
000 means no wait, 001 means wait to fill 1/8 of the BDMA Tx
buffer, 010 means wait to fill 2/8 of the buffer, 011 for 3/8 and
1xx for 4/8.
NOTE: If the last data of the frame arrives in BDMA Tx buffer,
the data transfer from the BDMA Tx buffer to the MAC Tx
FIFO starts immediately, regardless of the level of these bits.
Buffered DMA transmit control register
Description
Description
ETHERNET CONTROLLER
Reset Value
0x00000000
7-23