h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 112

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h8s-2161b

Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 2 CPU
Rev. 3.00 Mar 21, 2006 page 58 of 788
REJ09B0300-0300
Notes: 1.
RES = high
Exception-handling state
Bus-released state
2.
3.
Reset state *
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 26, Power-Down Modes.
End of bus
request
End of
exception
handling
1
Figure 2.13 State Transitions
Bus
request
External interrupt
request
STBY = high, RES = low
Request for
exception
handling
Program execution
End of bus request
Bus request
state
Interrupt
request
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Hardware standby mode *
Software standby mode
Power-down state *
Sleep mode
3
2

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