h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 581

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

HIRQ Setting/Clearing Conflict: If there is conflict between a P4DR or PBODR read/write by
the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the
host, clearing by the host is held pending during the P4DR or PBODR read/write by the CPU.
P4DR or PBODR clearing is executed after completion of the read/write.
18.6
18.6.1
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol must be followed to implement necessary functions
and avoid data contention. For example, if the host and slave processors try to access the same
input or output data register simultaneously, the data will be corrupted. Interrupts can be used to
design a simple and effective protocol.
Also, if two or more of pins CS1 to CS4 are driven low simultaneously in attempting IDR or ODR
access, signal contention will occur within the chip, and a through-current may result. This usage
must therefore be avoided.
18.6.2
XBS operation can be enabled or disabled using the module stop control register. The initial
setting is for XBS operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 26, Power-Down Modes.
Usage Notes
Note on Host Interface
Module Stop Mode Setting
Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 527 of 788
REJ09B0300-0300