h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 630

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 19 Host Interface LPC Interface (LPC)
Table 19.8 summarizes the methods of setting and clearing these bits, and figure 19.8 shows the
processing flowchart.
Table 19.8 HIRQ Setting and Clearing Conditions
Host Interrupt
HIRQ1
(independent
from IEDIR)
HIRQ12
(independent
from IEDIR)
SMI
(IEDIR = 0)
SMI
(IEDIR = 1)
HIRQi
(i = 6, 9 to 11)
(IEDIR = 0)
HIRQi
(i = 6, 9 to 11)
(IEDIR = 1)
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Setting Condition
Internal CPU writes to ODR1, then reads
0 from bit IRQ1E1 and writes 1
Internal CPU writes to ODR1, then reads
0 from bit IRQ12E1 and writes 1
Internal CPU
• writes to ODR2, then reads 0 from bit
• writes to ODR3, then reads 0 from bit
• writes to TWR15, then reads 0 from bit
Internal CPU
• reads 0 from bit SMIE2, then writes 1
• reads 0 from bit SMIE3A, then writes 1
• reads 0 from bit SMIE3B, then writes 1
Internal CPU
• writes to ODR2, then reads 0 from bit
• writes to ODR3, then reads 0 from bit
Internal CPU
• reads 0 from bit IRQiE2, then writes 1
• reads 0 from bit IRQiE3, then writes 1
SMIE2 and writes 1
SMIE3A and writes 1
SMIE3B and writes 1
IRQiE2 and writes 1
IRQiE3 and writes 1
Clearing Condition
Internal CPU writes 0 to bit IRQ1E1,
or host reads ODR1
Internal CPU writes 0 to bit IRQ12E1,
or host reads ODR1
Internal CPU
• writes 0 to bit SMIE2, or host
• writes 0 to bit SMIE3A, or host
• writes 0 to bit SMIE3B, or host
Internal CPU
• writes 0 to bit SMIE2
• writes 0 to bit SMIE3A
• writes 0 to bit SMIE3B
Internal CPU
• writes 0 to bit IRQiE2, or host
• CPU writes 0 to bit IRQiE3, or host
Internal CPU
• writes 0 to bit IRQiE2
• writes 0 to bit IRQiE3
reads ODR2
reads ODR3
reads TWR15
reads ODR2
reads ODR3