h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 478

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.3.5
ICCR controls the I
Bit
7
6
5
4
Rev. 3.00 Mar 21, 2006 page 424 of 788
REJ09B0300-0300
Bit Name
ICE
IEIC
MST
TRS
I
2
C Bus Control Register (ICCR)
2
C Bus Interface (IIC) (Optional)
Initial Value R/W
0
0
0
0
2
C bus interface and performs interrupt flag confirmation.
R/W
R/W
R/W
R/W
Description
I
0: I
1: I
I
0: Disables interrupts from the I
1: Enables interrupts from the I
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I
format. In slave receive mode with I
R/W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit mode
automatically by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
interface module internal state is initialized. SAR and
SARX can be accessed.
operation, and the ports function as the SCL and SDA
input/output pins. ICMR and ICDR can be accessed.
CPU
CPU.
2
2
C bus interface modules are stopped and I
C bus interface modules can perform transfer
2
2
C bus interface to the
C bus interface to the
2
C bus format, the
2
C bus
2
C bus