h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 473

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h8s-2161b

Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
16.3.3
SARX sets the second slave address and selects the communication format. In slave mode,
transmit/receive operations by the DTC are possible when the received address matches the
second slave address. If the LSI is in slave mode with the I
bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after
a start condition, the LSI operates as the slave device specified by the master device. SARX can be
accessed only when the ICE bit in ICCR is cleared to 0.
Bit
7
6
5
4
3
2
1
0
Bit Name
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
Second Slave Address Register (SARX)
Initial Value R/W
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Second Slave Address 6 to 0
Set the second slave address.
Format Select X
Selects the communication format together with the FS bit
in SAR and the SW bit in DDCSWR. Refer to table 16.2.
Section 16 I
Rev. 3.00 Mar 21, 2006 page 419 of 788
2
C bus format selected, when the FSX
2
C Bus Interface (IIC) (Optional)
REJ09B0300-0300

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