h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 679

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written
Reprogram Data Computation Table
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of z1 s or z2 s is applied according to the progress of the programming operation. See note 7 for details of the pulse widths. When writing of
6. The values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N are shown in sections 28.1.6 and 28.2.6, Flash Memory Characteristics.
Original Data
to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a z3 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
(D)
0
0
1
1
Note: 7. Write Pulse Width
Note: Use a z3 s write pulse for additional programming.
Number of Writes n
Verify Data
Write pulse application subroutine
(V)
Wait (z1) s, (z2) s or (z3) s
1000
0
1
0
1
998
999
10
11
12
13
Reprogram data storage
Clear PSU bit in FLMCR2
1
2
3
4
5
6
7
8
9
Additional-programming
Sub-Routine Write Pulse
Set PSU bit in FLMCR2
Program data storage
Clear P bit in FLMCR1
Set P bit in FLMCR1
data storage area
area (128 bytes)
area (128 bytes)
(128 bytes)
Reprogram Data
WDT enable
Disable WDT
Wait (α) s
Wait (γ) s
Wait (β) s
RAM
End Sub
(X)
1
0
1
1
Figure 23.11 Program/Program-Verify Flowchart
Write Time (z) s
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
*
6
*
*
*
*
6
5
6
6
Comments
*
6
Increment address
Additional-Programming Data Computation Table
Successively write 128-byte data from additional-
Apply write pulse (Additional programming) z3 s
programming data area in RAM to flash memory
Reprogram
NG
Data (X')
Transfer reprogram data to reprogram data area
Additional-programming data computation
Transfer additional-programming data to
0
0
1
1
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Apply
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
Verify Data
End of programming
write pulse z1
Read verify data
(V)
Wait (x) s
Write data =
OK
Wait (η) s
OK
Wait (θ) s
Rev. 3.00 Mar 21, 2006 page 625 of 788
Wait (γ) s
Wait (ε) s
verify data?
0
1
0
1
OK
128-byte
START
m = 0 ?
6 n ?
m = 0
n = 1
6 n?
OK
OK
Sub-Routine-Call
Programming Data (Y)
s or z2 s
Additional-
NG
NG
NG
0
1
1
1
NG
*
*
*
*
*
See note 7 for pulse width
*
*
*
*
*
6
6
4
1
6
6
6
6
3
2
*
*
4
4
*
*
m = 1
1
3
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
*
6
Clear SWE bit in FLMCR1
Programming failure
Wait (θ) s
n
REJ09B0300-0300
(N)?
Comments
Section 23 ROM
OK
NG
n
n + 1
*
6