h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 411
h8s-2161b
Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2161B.pdf
(845 pages)
- Current page: 411 of 845
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14.6.2
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 14.7 shows this operation.
14.6.3
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
14.6.4
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
Conflict between Timer Counter (TCNT) Write and Increment
Changing Values of CKS2 to CKS0 Bits
Switching between Watchdog Timer Mode and Interval Timer Mode
Address
Internal write signal
TCNT input clock
TCNT
Figure 14.7 Conflict between TCNT Write and Increment
TCNT write cycle
T
1
N
T
2
Rev. 3.00 Mar 21, 2006 page 357 of 788
Section 14 Watchdog Timer (WDT)
Counter write data
M
REJ09B0300-0300
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