h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 572

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 18 Host Interface X-Bus Interface (XBS)
18.3.5
STR indicates status information during host interface processing.
Bit
7 to 4 DBU
3
2
1
0
Note:
Rev. 3.00 Mar 21, 2006 page 518 of 788
REJ09B0300-0300
Bit Name
C/D
DBU
IBF
OBF
* Only 0 can be written, to clear the flag.
Status Register (STR)
Initial
Value
All 0
0
0
0
0
Slave
R/W
R
R/W
R
R/(W) *
R/W
R
R
Host
R
R
R
The user can use these bits as necessary.
Command/Data
Receives the HA0 input when the host processor
writes to IDR, and indicates whether IDR
contains data or a command.
0: Contents of input data register (IDR) are data
1: Contents of input data register (IDR) are a
The user can use these bits as necessary.
This bit is an internal interrupt source to the slave
processor (this LSI).
The IBF flag setting and clearing conditions are
different when the fast A20 gate is used. For
details see table 18.5.
[Clearing Condition]
0: When the slave processor reads IDR
[Setting Condition]
1: When the host processor writes to IDR
Output Buffer Full
[Clearing Condition]
0: When the host processor reads ODR or the
[Setting Condition]
1: When the slave processor writes to ODR
Description
Defined by User
Defined by User
Input Buffer Full
command
slave writes 0 in the OBF bit