h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 322

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h8s-2161b

Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 11 16-Bit Free-Running Timer (FRT)
11.3.8
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer
mode, and selects the FRC clock source.
Bit
7
6
5
4
3
2
Rev. 3.00 Mar 21, 2006 page 268 of 788
REJ09B0300-0300
Bit Name
IEDGA
IEDGB
IEDGC
IEDGD
BUFEA
BUFEB
Timer Control Register (TCR)
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Selects the rising or falling edge of the input capture A
signal (FTIA).
0: Capture on the falling edge of FTIA
1: Capture on the rising edge of FTIA
Selects the rising or falling edge of the input capture B
signal (FTIB).
0: Capture on the falling edge of FTIB
1: Capture on the rising edge of FTIB
Selects the rising or falling edge of the input capture C
signal (FTIC).
0: Capture on the falling edge of FTIC
1: Capture on the rising edge of FTIC
Selects the rising or falling edge of the input capture D
signal (FTID).
0: Capture on the falling edge of FTID
1: Capture on the rising edge of FTID
Selects whether ICRC is to be used as a buffer register
for ICRA.
0: ICRC is not used as a buffer register for ICRA
1: ICRC is used as a buffer register for ICRA
Selects whether ICRD is to be used as a buffer register
for ICRB.
0: ICRD is not used as a buffer register for ICRB
1: ICRD is used as a buffer register for ICRB
Input Edge Select A
Input Edge Select B
Input Edge Select C
Input Edge Select D
Buffer Enable A
Buffer Enable B

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