h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 33

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

18.6 Usage Notes ...................................................................................................................... 527
Section 19 Host Interface LPC Interface (LPC)
19.1 Features ............................................................................................................................. 529
19.2 Input/Output Pins .............................................................................................................. 531
19.3 Register Descriptions ........................................................................................................ 532
19.4 Operation .......................................................................................................................... 562
19.5 Interrupt Sources............................................................................................................... 575
19.6 Usage Notes ...................................................................................................................... 577
Section 20 D/A Converter
20.1 Features ............................................................................................................................. 579
20.2 Input/Output Pins .............................................................................................................. 580
20.3 Register Descriptions ........................................................................................................ 580
20.4 Operation .......................................................................................................................... 582
20.5 Usage Note........................................................................................................................ 583
18.5.1 IBF1, IBF2, IBF3, and IBF4 ................................................................................ 525
18.5.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 525
18.6.1 Note on Host Interface ......................................................................................... 527
18.6.2 Module Stop Mode Setting .................................................................................. 527
19.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)................................. 533
19.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)................................. 540
19.3.3 LPC Channel 3 Address Register (LADR3) ........................................................ 543
19.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 544
19.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)................................................... 545
19.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) .................................... 545
19.3.7 Status Registers 1 to 3 (STR1 to STR3)............................................................... 545
19.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ............................... 552
19.3.9 Host Interface Select Register (HISEL) ............................................................... 561
19.4.1 Host Interface Activation ..................................................................................... 562
19.4.2 LPC I/O Cycles .................................................................................................... 562
19.4.3 A20 Gate .............................................................................................................. 565
19.4.4 Host Interface Shutdown Function (LPCPD)....................................................... 568
19.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) .................................... 572
19.4.6 Host Interface Clock Start Request (CLKRUN) .................................................. 574
19.5.1 IBFI1 to IBFI3, and ERRI.................................................................................... 575
19.5.2 SMI, HIRQ1, HIRQ6, HIRQ9 to HIRQ12 .......................................................... 575
19.6.1 Module Stop Mode Setting .................................................................................. 577
19.6.2 Notes on Using Host Interface ............................................................................. 577
20.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 580
20.3.2 D/A Control Register (DACR) ............................................................................ 581
................................................................................................. 579
Rev. 3.00 Mar 21, 2006 page xxxiii of liv
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