h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 216

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Data Transfer Controller (DTC)
Table 7.5
Mode
Normal
Repeat
Block transfer
N: Block size (initial setting of CRAH and CRAL)
Table 7.6
The number of execution states is calculated from using the formula below. Note that
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
Rev. 3.00 Mar 21, 2006 page 162 of 788
REJ09B0300-0300
Bus width
Access states
Execution
status
Object to be Accessed
Number of execution states = I · S
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation S
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
S
S
S
S
S
S
I
J
K
K
L
L
M
Register Information
Read/Write
J
6
6
6
RAM
Chip
On-
32
—
1
1
1
1
1
1
I
+
ROM
Chip
On-
16
—
1
1
1
1
1
1
(J · S
On-Chip I/O
J
Registers
—
—
8
2
2
4
2
4
+ K · S
Data Read
K
1
1
N
16
K
—
—
2
2
2
2
2
+ L · S
1
—
L
2
4
2
4
2
4
) + M · S
Data Write
L
1
1
N
External Devices
8
6 + 2m
6 + 2m
6 + 2m
3 + m
3 + m
—
3
M
—
Internal
Operations
M
3
3
3
2
2
2
2
2
2
is the sum
16
3 + m
3 + m
3 + m
3 + m
3 + m
—
3