h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 120

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 3 MCU Operating Modes
Bit
2
1
0
3.2.3
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Rev. 3.00 Mar 21, 2006 page 66 of 788
REJ09B0300-0300
Bit Name
NMIEG
HIE
RAME
Serial Timer Control Register (STCR)
Initial Value
0
0
1
R/W
R/W
R/W
R/W
Description
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
1: An interrupt is requested at the rising edge of NMI
Host Interface Enable
Controls CPU access to the host interface registers
(HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2),
the keyboard matrix interrupt and MOS input pull-up
control registers (KMIMR, KMPCR, and KMIMRA), the
8-bit timer (TMR_X and TMR_Y) registers
(TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and
TCORB_X), and the timer connection registers
(TCONRI, TCONRO, TCONRS, and SEDGR).
0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
input
input
to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X
and TMR_Y) registers and timer connection
registers is permitted
to H'(FF)FFFF, CPU access to host interface
registers and keyboard matrix interrupt and MOS
input pull-up control registers is permitted