h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 406

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 14 Watchdog Timer (WDT)
14.4
14.4.1
To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the
WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a
system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this
LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the
RESO pin for 132 states, as shown in figure 14.2. If the RST/NMI bit is cleared to 0, when the
TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin
remains high.
An internal reset request from the watchdog timer and a reset input from the RES pin are
processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If
a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT
overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Rev. 3.00 Mar 21, 2006 page 352 of 788
REJ09B0300-0300
Operation
Watchdog Timer Mode