h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 602

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 19 Host Interface LPC Interface (LPC)
Bit
1
0
Note:
Rev. 3.00 Mar 21, 2006 page 548 of 788
REJ09B0300-0300
Bit Name Initial Value Slave Host Description
IBF2
OBF2
* Only 0 can be written to clear the flag.
0
0
R
R/(W) * R
R/W
R
Input Buffer Full
Set to 1 when the host processor writes to IDR. This
bit is an internal interrupt source to the slave
processor (this LSI). IBF is cleared to 0 when the
slave processor reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 19.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O write
cycle
Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR