h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 114

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
Prior to executing BCLR:
Input/output
Pin state
DDR
DR
BCLR instruction executed:
After executing BCLR:
Input/output
Pin state
DDR
DR
Operation:
1. When the BCLR instruction is executed, first the CPU reads P4DDR.
2. The CPU clears bit 0 of the read data to 0, changing data to H'FE.
3. The CPU writes H'FE to DDR, completing execution of BCLR.
As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin.
However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins.
Rev. 3.00 Mar 21, 2006 page 60 of 788
REJ09B0300-0300
BCLR
Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a
value of H'3F, but the value read by the CPU is H'FF.
#0,
P47
Input
Low
level
0
1
P47
Output
Low
level
1
1
@P4DDR
P46
Input
High
level
0
0
P46
Output
High
level
1
0
The BCLR instruction is executed for DDR in port 4.
P45
Output
Low
level
1
0
P45
Output
Low
level
1
0
P44
Output
Low
level
1
0
P44
Output
Low
level
1
0
P43
Output
Low
level
1
0
P43
Output
Low
level
1
0
P42
Output
Low
level
1
0
P42
Output
Low
level
1
0
P41
Output
Low
level
1
0
P41
Output
Low
level
1
0
P40
Output
Low
level
1
0
P40
Input
High
level
0
0