h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 329
h8s-2161b
Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2161B.pdf
(845 pages)
- Current page: 329 of 845
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Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture
input signal arrives, input capture is delayed by one system clock ( ). Figure 11.10 shows the
timing when BUFEA = 1.
FTIA
Input capture
signal
FRC
ICRA
ICRC
FTIA
Input capture
signal
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)
CPU read cycle of ICRA or ICRC
M
m
Figure 11.9 Buffered Input Capture Timing
T 1
n
T 2
M
n
n + 1
Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Mar 21, 2006 page 275 of 788
N
M
n
N
n
REJ09B0300-0300
N + 1
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