HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 138

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6. Interrupt Controller (INTC)
Rev.4.00 Mar. 27, 2008 Page 94 of 882
REJ09B0108-0400
Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU
Copy accept-interrupt
Branch to exception
execution state
Save SR to stack
Save PC to stack
IRQOUT = high
Read exception
IRQOUT = low
level to I3 to I0
service routine
Interrupt?
vector table
Program
1. IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1).
2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared
by a power-on reset or a manual reset.
NMI?
Yes
Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the IRQOUT pin holds low level.
Yes
No
No
User break?
*1
*2
Yes
Figure 6.3 Interrupt Sequence Flowchart
No
interrupt?
H-UDI
Yes
Yes
No
interrupt?
level 14?
Level 15
I3 to I0 ≤
No
Yes
Yes
No
interrupt?
level 13?
Level 14
I3 to I0 ≤
No
Yes
Yes
No
interrupt?
I3 to I0 =
level 0?
Level 1
No
Yes
No