HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 532

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HD6417144

Manufacturer Part Number
HD6417144
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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14. I
Rev.4.00 Mar. 27, 2008 Page 488 of 882
REJ09B0108-0400
Bit Bit Name Initial Value R/W
2
1
AAS
ADZ
2
C Bus Interface (IIC) Option
0
0
R/(W)* Slave Address Detection Flag
R/(W)* General Call Address Detection Flag
Description
When the first frame after the start condition matches the SVA6
to SVA0 bits of SAR or when the general-call address (H'00) is
detected in the I
[Setting condition]
[Clearing conditions]
In the I
general-call address (H'00) is detected in the first frame
after the start condition.
[Setting condition]
[Clearing conditions]
When the general call address is detected while FS = 1 and
FSX = 0, the ADZ flag is set to 1 but the general call
address is not identified (the AAS flag is not set to 1).
Detection of the slave address or general call address (one
frame, including the R/W bit, is H'00) while in the slave-
receive mode and FS = 0.
Writing of data to ICDR (during transmission) or reading of
data from ICDR (during reception)
Writing of 0 to this bit after reading it as 1
Entering the master mode
Detection of the general call address (one frame,
including R/W bit, is H'00) in the slave-receive mode
(FSX = 0 or FS = 0).
Writing of data to ICDR (during transmission) or reading
of data from ICDR (during reception).
Writing 0 to this bit after reading it as 1
Entering the master mode
2
C bus format in the slave-reception mode, the
2
C bus format in the slave receive mode.

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