HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 230

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

10. Direct Memory Access Controller (DMAC)
Figure 10.3 (2) shows the changes in priority levels when transfer requests are issued
simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on
channel 0. The DMAC operates in the following manner under these circumstances:
1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is conducted
3. A transfer request is issued for channel 1 during a transfer on channel 0 (channels 1 and 3 are
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer
6. When the channel 1 transfer ends, channel 1 shifts to the lowest priority level.
7. Channel 3 transfer begins.
8. When the channel 3 transfer ends, channel 3 and channel 2 priority levels are lowered, giving
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REJ09B0108-0400
first (channel 3 is on transfer standby).
on transfer standby).
comes first (channel 3 is on transfer standby).
channel 3 the lowest priority.
Figure 10.3 (2) Example of Changes in Priority in Round Robin Mode
Transfer request
Issued for
Issued for channel 1
channels 0 and 3
Channel waiting
1,3
3
3
None
DMAC operation
Channel 0
transfer begins
Channel 0
transfer ends
Channel 1
transfer begins
Channel 1
transfer ends
Channel 3
transfer begins
Channel 3
transfer ends
Change of
priority
Change of
priority
Change of
priority
Channel priority
0 > 1 > 2 > 3
1 > 2 > 3 > 0
2 > 3 > 0 > 1
0 > 1 > 2 > 3