HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 147

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.2
The UBC has the following registers. For details on register addresses and register states during
each processing, refer to section 25, List of Registers.
• User break address register H (UBARH)
• User break address register L (UBARL)
• User break address mask register H (UBAMRH)
• User break address mask register L (UBAMRL)
• User break bus cycle register (UBBR)
• User break control register (UBCR)
7.2.1
The user break address register (UBAR) consists of two registers: user break address register H
(UBARH) and user break address register L (UBARL). Both are 16-bit readable/writable registers.
UBARH specifies the upper bits (bits 31 to 16) of the address for the break condition, while
UBARL specifies the lower bits (bits 15 to 0).
The initial value of UBAR is H'00000000.
• UBARH Bits 15 to 0: specifies user break address 31 to 16 (UBA31 to UBA16)
• UBARL Bits 15 to 0: specifies user break address 15 to 0 (UBA15 to UBA0)
7.2.2
The user break address mask register (UBAMR) consists of two registers: user break address mask
register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH specifies whether to mask any of the break address bits set
in UBARH, and UBAMRL specifies whether to mask any of the break address bits set in UBARL.
• UBAMRH Bits 15 to 0: specifies user break address mask 31 to 16 (UBM31 to UBM16)
• UBAMRL Bits 15 to 0: specifies user break address mask 15 to 0 (UBM15 to UBM0)
Register Descriptions
User Break Address Register (UBAR)
User Break Address Mask Register (UBAMR)
Rev.4.00 Mar. 27, 2008 Page 103 of 882
7. User Break Controller (UBC)
REJ09B0108-0400