HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 288

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.
11.3.4
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU has five TIER registers, one for each channel.
Rev.4.00 Mar. 27, 2008 Page 244 of 882
REJ09B0108-0400
Bit
7
6
5
4
3
Multi-Function Timer Pulse Unit (MTU)
Bit Name
TTGE
—
TCIEU
TCIEV
TGIED
Timer Interrupt Enable Register (TIER)
0
0
0
0
Initial Value
1
R/W
R/W
R
R/W
R/W
R/W
Description
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This bit is always read as 1. The write value should
always be 1.
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0 and the write value should always be 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 3 is reserved. It is always
read as 0 and the write value should always be 0.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled