HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 309

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Example of Synchronous Operation Setting Procedure:
Figure 11.11 shows an example of the synchronous operation setting procedure.
Example of Synchronous Operation: Figure 11.12 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are
performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM
cycle.
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to,
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
<Synchronous presetting>
Synchronous presetting
Synchronous operation
operation.
the same value is simultaneously written to the other TCNT counters.
Figure 11.11
Set synchronous
Set TCNT
operation
selection
Example of Synchronous Operation Setting Procedure
[1]
[2]
Synchronous clearing
<Counter clearing>
source generation
clearing source
Select counter
Start count
channel?
Clearing
Yes
11.
Rev.4.00 Mar. 27, 2008 Page 265 of 882
No
[3]
[5]
Multi-Function Timer Pulse Unit (MTU)
<Synchronous clearing>
Set synchronous
counter clearing
Start count
REJ09B0108-0400
[4]
[5]