HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 748
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HD6417144
Manufacturer Part Number
HD6417144
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417144.pdf
(930 pages)
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22. User Debugging Interface (H-UDI)
22.5
• The registers are not initialized in software standby mode. If TRST is set to 0 in software
• The frequency of TCK must be lower than that of the peripheral module clock (Pφ). For
• In serial data transfer, data input/output starts with the LSB. Figure 22.5 shows serial data
• If the H-UDI serial transfer sequence is disrupted, a TRST reset must be executed. Transfer
• The TDO output timing is from the rise of TCK.
• In the Shift-IR state, the lower 2 bits of the output data from TDO (the IR status word) may not
• If more than 32 bits are serially transferred, serial data exceeding 32 bits output from TDO
• The TDI pin must not be in the high-impedance state.
Rev.4.00 Mar. 27, 2008 Page 704 of 882
REJ09B0108-0400
standby mode, bypass mode will be entered.
details, see section 26, Electrical Characteristics.
input/output.
should then be retried, regardless of the transfer operation.
always be 01.
should be ignored.
Usage Notes
TDO
TDI
Shift register
Figure 22.5 Serial Data Input/Output
SDIR, SDSR,
SDDRH/SDDRL
31
30
1
0
Serial data
input/output is in
LSB-first order.
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