HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 374

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HD6417144

Manufacturer Part Number
HD6417144
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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11.
11.7.12 Counter Value during Complementary PWM Mode Stop
When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM
mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000.
When restarting complementary PWM mode, counting begins automatically from the initialized
state. This explanatory diagram is shown in figure 11.80.
When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to
the initial values.
11.7.13 Buffer Operation Setting in Complementary PWM Mode
In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting
register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3,
TGRA_4, and TGRB_4).
In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit
settings BFA and BFB of TMDR_3. When TMDR_3’s BFA bit is set to 1, TGRC_3 functions as a
buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for
TGRA_4, while the TCBR functions as the TCDR’s buffer register.
Rev.4.00 Mar. 27, 2008 Page 330 of 882
REJ09B0108-0400
Multi-Function Timer Pulse Unit (MTU)
Figure 11.80
TGRA_3
TCDR
TDDR
H'0000
Complementary PWM
TCNT_3
Counter Value during Complementary PWM Mode Stop
mode operation
TCNT_4
Counter
operation stop
Complementary
PMW restart
Complementary PWM
mode operation

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