HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 527

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 14.4 The Relationship between Flags and Transfer States (Master Mode)
[Legend]
0:
1:
⎯:
0
1
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0↓
1
↓
↑
:
:
1
1
⎯
1
1
1
1
1
1
0
0
0
0
0
0↓
⎯
0-state retained
1-state retained
Previous state retained
Cleared to 0
Set to 1
0
1↑
1
1
1
1
1
1
1
1
1
1
1
1
1
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1↑
⎯
⎯
1↑
⎯
⎯
⎯
1↑
1↑
⎯
⎯
⎯
1↑
⎯
⎯
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1↑ 0
0
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
1↑
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Rev.4.00 Mar. 27, 2008 Page 483 of 882
ICDRF ICDRE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1↑
0↓
1
0↓
1↑
⎯
⎯
14. I
0
1↑
⎯
⎯
1↑
0↓
1
0↓
1↑
⎯
⎯
⎯
⎯
⎯
⎯
0↓
2
C Bus Interface (IIC) Option
Idle state (flag clearing
required)
Start condition detected
Wait state
Transmission end (ACKE = 1
and ACKB = 1)
Transmission end with
ICDRE = 0
ICDR write with the above
state
Transmission end with
ICDRE = 1
ICDR write with the above
state or after start condition
detected
Automatic data transfer from
ICDRT to ICDRS with the
above state
Reception end with ICDRF =
0
ICDR read with the above
state
Reception end with ICDRF =
1
ICDR read with the above
state
Automatic data transfer from
ICDRS to ICDRR with the
above state
Arbitration lost
Stop condition detected
State
REJ09B0108-0400