HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 559

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The following description gives the procedures for and operations of receiving data in slave
receive mode.
1. Perform initialization according to the procedure described in section 14.4.2, Initialization.
2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read ICDR and then clear the
3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
4. When the slave address matches the address in the first frame following the start condition
5. The slave devise returns the data set in the ACKB bit as an acknowledgement at the 9th cycle
6. The IRIC flag is set to 1 at the 9th cycle of the clock. At this time, if the IEIC bit is set to 1, an
7. At the rising edge of the 9th cycle of the clock, the receive data is transferred from ICDRS to
8. Confirm that the STOP bit is cleared to 0, and then clear the IRIC flag to 0.
9. When the data to be read next is in two frames before the final receive frame, ensure at least
10. Confirm that the ICDRF flag is set to 1, and then read ICDR.
11. If the receive data is transferred from ICDRS to ICDRR at the rising edge of the 9th cycle of
12. After the stop condition (when SCL is high, the SDA is changed from low to high) is detected,
13. Clear IRIC flag to 0.
Set slave receive mode by clearing the MST and TRS bits to 0. Set the HNDS and ACKB bits
to 0. To confirm the receive completion, clear the IRIC flag in ICCR to 0.
IRIC flag to 0.
to 1. The master device then outputs the 7-bit slave address and transmit/receive direction
(R/W) data in synchronization with the transmit clock pulses.
generation, the slave device operates as the slave devise specified by the master device. When
the 8th bit of data (R/W) is 0, the TRS bit remains 0 and slave receive operation is performed.
When the 8th bit of data (R/W) is 1, the TRS bit is set to 1 and slave transmit operation is
performed.
When addresses do not match, data receive operation is not performed until the next start
condition is detected.
of the receive frame of the clock.
interrupt request is generated for the CPU.
If the AASX bit is also set to 1, the IRTR flag is set to 1.
ICDRR and the ICDRF flag is set to 1.
one frame of wait time. Set the ACKB bit to 1 after the 9th cycle of the receive frame
preceding the final receive frame.
After ICDR has been read, the ICDRF flag is cleared to 0.
the clock or ICDR read, IRIC and ICDRF flags are set to 1.
the BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. At this time, if the
STOPIM bit is cleared to 0, the IRIC flag is set to 1. In this case, read the final receive data as
described in step 14.
Receive operation can be continued by repeating steps 9 to 13
Rev.4.00 Mar. 27, 2008 Page 515 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400