HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 756

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HD6417144

Manufacturer Part Number
HD6417144
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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23. Advanced User Debugger (AUD)
23.4
23.4.1
In this mode, all the modules connected to this LSI's internal or external bus can be read and
written to, allowing RAM monitoring and tuning to be carried out.
When an address is written to AUDATA externally, the data corresponding to that address is
output. If an address and data are written to AUDATA, the data is transferred to the address.
23.4.2
The AUD latches the AUDATA input when AUDSYNC is asserted. The following AUDATA
input format should be used.
Rev.4.00 Mar. 27, 2008 Page 712 of 882
REJ09B0108-0400
RAM Monitor Mode
Overview
Communication Protocol
Input format
0000
Command
Figure 23.4 AUDATA Input Format
DIR
Spare bits (4 bits): b'0000
A3 to A0
Fixed at 1
Bit 3
Address
. . . . . .
0: Read
1: Write
Bit 2
A31 to A28 D3 to D0
Bit 1
00: Byte
01: Word
10: Longword
Data (in case of write only)
Bit 0
B write: n = 7
W write: n = 15
L write: n = 31
. . . . . .
Dn to Dn-3

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