HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 201

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.6.3
Idle cycles can be inserted to prevent extension of the RD or WRxx signal assert period beyond
the length of the CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This allows
for flexible interfaces with external circuitry. The timing is shown in figure 9.6. Th and Tf cycles
are added respectively before and after the normal cycle. Only CSn is asserted in these cycles; RD
and WRxx signals are not. Further, data is extended up to the Tf cycle, which is effective for gate
arrays and the like, which have slower write operations.
CS Assert Period Extension
Read
Write
Figure 9.6 CS Assert Period Extension Function
Address
DACK
WRxx
Data
Data
CSn
RD
CK
Th
T1
T2
Rev.4.00 Mar. 27, 2008 Page 157 of 882
Tf
9. Bus State Controller (BSC)
REJ09B0108-0400