HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 484

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13. Serial Communication Interface (SCI)
13.5.2
Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
13.12 shows an example of SCI operation for multiprocessor format reception.
Rev.4.00 Mar. 27, 2008 Page 440 of 882
REJ09B0108-0400
MPIE
RDRF
RDR
value
RxD
MPIE
RDRF
RDR
value
RxD
Multiprocessor Serial Data Reception
1
1
Start
bit
Start
bit
0
0
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
MPIE = 0
MPIE = 0
D0
D0
Figure 13.12 Example of SCI Operation in Reception
ID1
D1
D1
Data (ID1)
Data (ID2)
RXI interrupt
request
(multiprocessor
interrupt)
generated
RXI interrupt
request
(multiprocessor
interrupt)
generated
D7
D7
(a) Data does not match station’s ID
(b) Data matches station’s ID
MPB
MPB
1
1
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
Stop
bit
Stop
bit
1
1
Start
bit
Start
bit
0
0
D0
D0
If not this station’s ID,
MPIE bit is set to 1
again
Matches this station’s ID,
so reception continues,
and data is received in RXI
interrupt processing routine
D1
D1
Data (Data1)
Data (Data2)
ID2
ID1
D7
D7
MPB
MPB
0
0
RXI interrupt request is
not generated, and RDR
retains its state
Stop
bit
Stop
bit
1
1
MPIE bit is set to 1
again
Idle state
(mark state)
Idle state
(mark state)
Data2
1
1